A10 IC封装体制程芯片厚度对金线偏移影响之研究

IC封装体制程芯片厚度对金线偏移影响之研究

A study of chip thickness effect on the wire sweep of IC packages

徐因德、曾世昌

Yin-Te Hsu, Shi-Chang Tseng       

国立云林科技大学 机械工程研究所

Dept. of Mechanical Engineering, National Yunlin University of Science & Technology

中文摘要

由于半导体IC封装朝着轻、薄、短、小的方向发展，产品精密度的要求越来越高，而输出/入(I/O)讯号逐渐增加而使金线密度及数量相对增加，因塑料于充填过程中树脂流动会对金线产生拖曳力而产生金线偏移，当偏移量过大将可能导致IC内部短路功能失效发生，以BGA封装形态其封装技术上而言封装面积较传统小，属于金线数目较多且高密度集积化的封装形式，但仍须经由不断的实验测试中找出造成金线偏移的原因，但这往往须花费一大半的时间和金钱才能完成，如今拜计算机运算速度快速发展，藉由计算机来仿真流体于流动时的波前、压力、温度、熟化度…等分布情况，本文对于薄型微间距球栅数组集成电路TFBGA 60(Thin And Fine Pitch Ball Grid Array 60) IC封装形式进行充填过程之仿真分析，利用CAE 软件 Mlodex3D之仿真模压于不同芯片厚度搭配射出时间、射出压力、模具温度等条件改善充填过程中因树脂流动对金线产生拖曳力使金线产生的偏移量，并将仿真分析數据与实体X-ray 量测數据比较，结果十分相近，有助于提升模具设计质量并降低金线偏移量。

英文摘要

The trend for IC chips is toward lighter, thinner and smaller. This makes the precision requirements of I/O within the chips become higher and higher. The arrangement of wires becomes more condense and may lead to more severe wire sweep or even short-circuit problems. Although the Ball Grid Array (BGA) type package has been developed and tried to solve the mentioned problems, the real mold making and testing is so time and money consuming. The CAE simulation can help to reduce such cost before the metal is cut. Therefore, this work has used Moldex-3D IC package module to help the mold filling and wire sweep simulation. The processing parameters such as filling times, filling pressures, mold temperatures and chip thicknesses have been selected as the input factors in the Taguchi’s design of experiments. The values of wire sweep can be predicted and compared under the orthogonal array. The simulated results were compared to the experimental data measured through X-ray microscopy. Both results are quite close. The work done here is believed to help increase the quality of IC package mold design and reduce the amount of wire sweep. 

关键词:

芯片封装、金线偏移、模流分析、田口质量工程

PDF文档下载：A10.pdf